IEEE

Implementation of FIFO design using Verilog HDL to avoid data losses in transmission

Abstract: DFSR (Direct Feedback Shift Register) counters incorporate a network router switch through which the bundle enters. The parcel is then driven out through three result ports, each containing ...
IEEE

Multiplication-Free Lookup-Based CNN Accelerator Using Residual Vector Quantization and Its FPGA Implementation

Abstract: In this paper, a table lookup-based computing technique is proposed to perform convolutional neural network (CNN) inference without multiplication, and its FPGA implementation is ...